PIC18LF66K80-I/PT【PDF 43/351 页】MCU PIC ECAN 64KB FLASH 64TQFP

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2010-2012 Microchip Technology Inc.

DS39977F-page 137

PIC18F66K80 FAMILY

EXAMPLE 7-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

7.5.2

WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

7.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. If the write operation is interrupted

by a MCLR Reset or a WDT Time-out Reset during

normal operation, the user can check the WRERR bit

and rewrite the location(s) as needed.

7.5.4

PROTECTION AGAINST

SPURIOUS WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 28.0 “Special Features of the

CPU”

for more detail.

7.6

Flash Program Operation During

Code Protection

See Section 28.6 “Program Verification and Code

Protection”

for details on code protection of Flash

program memory.

TABLE 7-2:

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

PROGRAM_MEMORY

BSF

EECON1, EEPGD

; point to Flash program memory

BCF

EECON1, CFGS

; access Flash program memory

BSF

EECON1, WREN

; enable write to memory

BCF

INTCON, GIE

; disable interrupts

MOVLW

55h

Required

MOVWF

EECON2

; write 55h

Sequence

MOVLW

0AAh

MOVWF

EECON2

; write 0AAh

BSF

EECON1, WR

; start program (CPU stall)

BSF

INTCON, GIE

; re-enable interrupts

BCF

EECON1, WREN

; disable write to memory

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TBLPTRU

—

—bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

TBPLTRH

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

TABLAT

Program Memory Table Latch

INTCON

GIE/GIEH

PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

EECON2

EEPROM Control Register 2 (not a physical register)

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

IPR4

TMR4IP

EEIP

CMP2IP

CMP1IP

—

CCP5IP

CCP4IP

CCP3IP

PIR4

TMR4IF

EEIF

CMP2IF

CMP1IF

—

CCP5IF

CCP4IF

CCP3IF

PIE4

TMR4IE

EEIE

CMP2IE

CMP1IE

—

CCP5IE

CCP4IE

CCP3IE

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

Note 1:

Bit 21 of the TBLPTRU allows access to the device Configuration bits.

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